Reverse Engineering测试介绍
Overview | Process | Layout & Structure | T.A.T | |
|---|---|---|---|---|
class-S | Package Overview Bump & Pad Information Die Overview 1.0 week | Process Integration( simple analysis ) Process Tech. Node 1.0 week | Layer imaging depending on the number of layers & customer reply | base on the overall analysis : |
class-A | T.A.T reduction 0.5 week | Process Overview : Logic and/or SRAM ( TEM : Gate, Metal ) 1.5 week | Functional Blocking Memory Cell Type 0.5 week | base on the overall analysis : express 1.5 ~ 2.5 weeks |
class-B | 0.5 week | Process Overview : Logic and/or SRAM ( TEM : each module ) 2.5 week | Memory Bit Counting 2.0 week | base on the overall analysis : express 3.0 ~ 5.0 weeks |
class-c | Package Overview ( cross-section, EDX ) 1.5 week | Process Overview : Logic and/or SRAM ( details & material ) 5.5 week | Layout Extraction (simple) : Memory Cell (each layer) : simple circuit 3.0 week | base on the overall analysis : express 7.0 ~ 10 weeks |
The service price depends on the process technology, chip area, # of memory, T.A.T(express charge +5%~40%) and others.
- 上一个：不良分析
- 下一个：Conterfeit Analysis
